Laptop computers, personal digital assistants (PDAs), and other mobile devices often incorporate wireless local area network (WLAN) technology that typically operates using battery power. Therefore, it is important to minimize power dissipation in mobile devices to preserve battery life. Sometimes WLAN circuits are implemented as a system-on-chip (SOC).
Referring now to FIG. 1, an SOC 10 for a wireless network device includes modules 12 that communicate with each other over a system bus 14. The modules 12 include memory modules, processors, host interfaces, peripheral interfaces, local area network (LAN) interfaces, and/or other modules. The wireless network device may communicate with other external devices. For example, the wireless network device may communicate with an external radio frequency (RF) transmitter. Since the modules 12 communicate through a common system bus 14, most of the modules 12 are clocked at the same rate as the system bus 14 or at rates that are derived from the system bus 14 rate.
Only one of the modules 12 is allowed to access the system bus 14 at a given time. Since more than one of the modules 12 may simultaneously attempt to use the system bus 14, a bus arbiter module 16 determines which of the modules 12 has permission to use the system bus 14 at a given time. When one of the modules 12 requires use of the system bus 14, the module 12 requests permission from the bus arbiter module 16. The modules 12 request permission by asserting request signals 18 that are transmitted to the bus arbiter module 16.
Referring now to FIG. 2A, a request signal 26 from a requesting module remains high (or low) when the requesting module does not require use of the system bus 14. When the requesting module requires use of the system bus 14, the requesting module transitions to low (or high). During a write operation, the request signal 26 typically remains asserted until the end of the transaction. The bus arbiter module 16 detects the request signal 26 and instructs a target module to assert an acknowledge signal 28 when the requesting module is free to use the system bus 14.
Once the target module asserts the acknowledge signal 28, the requesting module begins transmitting data to the target module following a single clock cycle delay. At the end of the write transaction, the request signal 26 will transition to high (or low).
Referring now to FIG. 2B, in other bus architectures, the request signal 30 will transition to high (or low) when the acknowledge signal 32 is received. In this case, a last signal 34 is asserted to indicate the end of the transaction.
Referring now to FIG. 2C, during a read transaction, a request signal 36 typically does not remain asserted during the entire transaction. When the requesting module requires use of the system bus 14, the module asserts the request signal 36 by transitioning to low (or high). The bus arbiter module 16 detects the request signal and instructs the target module to assert an acknowledge signal 38. During a read transaction, it typically takes the target module time to retrieve the requested data. Therefore, the acknowledge signal 38 is only asserted for a single clock cycle.
At the end of the clock cycle both the request signal 36 and the acknowledge signal 38 transition to high (or low). This allows other modules 12 in the SOC 10 to use the system bus 14 while the target module retrieves the requested data. The target module asserts a read valid signal 40 to request permission to use the system bus 14. After the bus arbiter module 16 grants permission, the target module begins transmitting data to the requesting module. This is called a split-read process. The read valid signal 40 remains low (or high) while the target module transmits data. The read valid signal 40 transitions to high (or low) when the target module is finished transmitting data to the requesting module.
Power dissipation in an SOC is proportional to the clock frequency. Therefore, power dissipation is minimized by minimizing the clock frequency of the system bus in the SOC. A minimum sufficient clock frequency for an SOC is dependant on the amount of data movement and a number of current computations. Therefore, the minimum clock frequency that sufficiently supports all data traffic will change as the amount of data traffic changes.
In one conventional approach, a clock frequency of an SOC is set to a frequency that is sufficient to handle data traffic in a worst case scenario. However, in this case, power is unnecessarily dissipated when the data traffic in the SOC is lower.